1. Field of the Invention
The present invention relates to a data processor which subdivides one instruction into a plurality of internal codes by a decoder. More particularly, it relates to a data processor which, when decoding a multi-functional instruction executing multiple processings for plural operands, subdivides the instruction and outputs the decoded results, processes the subdivided decoded results in respective pipelining stages after the decoding stage of a pipelining mechanism to execute the multi-functional instructions at high efficiency.
2. Description of the Related Art
In a conventional data processor, there are multi-functional instructions such as an ENTER instruction for forming a stack frame and saving a register at an entrance of a subroutine in high-level languages, an EXITD instruction for releasing the stack frame and restoring the register at an exit of the subroutine in high-level languages, an LDM instruction which loads multiple data from memory to the registers, and an STM instruction which stores multiple data from registers into memory. These instructions were executed by microprograms so that the instructions were processed by successively executing the necessary processings by the microprogram.
Data processors which decompose one instruction into multiple processings by using the microprogram for execution have been known for a long time, for example, one is particularly described in chapter No. 5.5 of "Computer Architecture and Quantitative Approach," by J. L. Hennessy and D. A. Patterson, Morgan Kaufmann Publishers, Inc. 1990".
A data processor which decomposes the multi-functional instruction into multiple processings for execution by the microprogram is disclosed, for example, in the invention disclosed in Japanese Patent Application Laid-Open No. 2-231966(1990).
In the conventional data processor which decomposes the multi-functional instruction into multiple processings by the microprogram for execution as stated above, if an instruction pipelining mechanism is used the multi-functional instruction is processed in the execution stage, and in a stage where the address calculation of the operand is performed and in a stage where the operand is fetched, processings are not performed at all or hardly any processing is performed.
In the conventional data processor, multi-functional instructions are processed in three stages, preprocessing, actual processing, and after-processing, by the microprogram in the execution stage. The preprocessing and after-processing among them are not processings designated by the multi-functional instruction, but are overhead, independent upon hardware.
Specifically, in the multiple data loading instruction (LDM) for loading multiple operands data to the register from memory, in accordance with a register list indicated by a bit string of "1" and "0", as preprocessing of data transfer from the memory to the register which is the essential processing of the instruction, the register list, outputted from an instruction decoder must be transferred to a priority encoder.
In conventional data processors, the execution of multi-functional instructions requires preprocessing to analyze the data which serves as parameters for the instruction, such as a register list in a LDM instruction. The extra time required to do such preprocessing is overhead, and slows down the execution of such multi-functional instructions.
Also, in the case where the multiplication and addition are executed by one instruction, for example, in executing a combined instruction such as "MUL & ADD R0, R3, R2, R8" which designates two processings of multiplying data stored respectively in registers R0 and R3 to store the result into the register R3, and of adding data stored respectively in the registers R2 and R8 to store the result into the register R8, such a problem is encountered that the hardware volume of an instruction decoder which outputs control information for executing the two processings simultaneously increases.